Abstract: Digital signal filtering is used in many different fields, including communications, radar, navigation and others, because of its excellent performance and the ability to obtain accurate results using FIR and IIR filter

In this paper, we propose the design and implementation mechanism for FIR digital MBF based on the use of Cyclone II EP2C20F484C7 FPGA from ALTERA, placed on education and development board DE-1. The designed filter has the following parameters:

-Clock frequency: FCLK=50 MHz.
-Sampling frequency: fsam= 2 MHz.
-Pass bands of the multiband filter (MBF): (0 -50 KHz), (100 -150 KHz), (200 -250 KHz) , (300 -350 KHz).
-Stop bands of the multiband filter (MBF): (50-100 KHz), (150 -200 KHz), (250 -300 KHz) , (350 -1000 KHz).
-Type of input signal is sinusoidal of frequency: finp=25 KHz, 75 KHz ,125 KHz, 175 KHz, 225 KHz, 275 KHz, 325 KHz
and 375 KHz.
-The ROM capacity for the stored input signal samples is 8192X8 bits, and their values are positive within the range from
(0 to 255).
-Frequency range: (0.12 Hz…1 MHz).
-Frequency Resolution: (0.12 Hz).
- Signal amplitude (5V).
Digital designs using FPGA allow the system to be modified and developed to obtain better results through reprogramming according to the user's desire.

Keywords: digital filter, FIR, MBF, DDFS, FPGA.

Download: | DOI: 10.17148/IMRJR.2025.020605