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Design and Implementation of a Digital Laboratory Experiment to Obtain Lissajous Figures Using FPGA
Dr. Kamal Aboutabikh
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Abstract: In this paper, a two-output direct digital frequency synthesizer (DDFS) is designed to generate two sinusoidal signals: one with a reference signal with a zero initial phase, and the other with a phase control within a range of 0 to 360 degrees at a 45-degree angle. The first signal has two frequencies of 1 MHz or 2 MHz, while the second signal has three frequencies of 1 MHz , 2 MHz or 3 MHz .
The purpose of this design is to obtain Lissajous Figures for the frequency ratio between the first signal and the second signal is (1/1, 1/2, 1/3, 2/3), and the initial phase values of the second signal for each ratio takes the values (0, 45, 90, 135, 180, 225, 270, 315) degrees.
Also, we discuss a practical mechanism of a dual-output direct digital frequency synthesizer (DODDFS) using Cyclone II EP2C20F484C7 FPGA from ALTERA placed on education and development board DE-1 with the following parameters: -Output waveforms: sinusoidal.
-Frequency range: (3Hzβ¦..10 MHz).
-Frequency Resolution (3Hz).
-Signal amplitude (5V).
-With Reset of the DODDFS.
-Frequency of the generated signal for all types signals: (1 MHz, 2 MHz, 3 MHz).
-Phase shifts: (0,45,90,135,180,225,270,315) degrees.
Keywords: Lissajous Figures, DDFS, DODDFS, FPGA.
The purpose of this design is to obtain Lissajous Figures for the frequency ratio between the first signal and the second signal is (1/1, 1/2, 1/3, 2/3), and the initial phase values of the second signal for each ratio takes the values (0, 45, 90, 135, 180, 225, 270, 315) degrees.
Also, we discuss a practical mechanism of a dual-output direct digital frequency synthesizer (DODDFS) using Cyclone II EP2C20F484C7 FPGA from ALTERA placed on education and development board DE-1 with the following parameters: -Output waveforms: sinusoidal.
-Frequency range: (3Hzβ¦..10 MHz).
-Frequency Resolution (3Hz).
-Signal amplitude (5V).
-With Reset of the DODDFS.
-Frequency of the generated signal for all types signals: (1 MHz, 2 MHz, 3 MHz).
-Phase shifts: (0,45,90,135,180,225,270,315) degrees.
Keywords: Lissajous Figures, DDFS, DODDFS, FPGA.
How to Cite:
[1] Dr. Kamal Aboutabikh, βDesign and Implementation of a Digital Laboratory Experiment to Obtain Lissajous Figures Using FPGA,β International Multidisciplinary Research Journal Reviews (IMRJR) (IMRJR), DOI: 10.17148/IMRJR.2025.020801
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