Design and Implementation of a Digital Coherence BPSK Demodulator using FPGA

Abstract: JIn this paper, we propose the design and implementation mechanism for a digital coherence BPSK demodulator based on the use of Direct Digital Frequency Synthesizer (DDFS) and digital filter using Cyclone II EP2C20F484C7 FPGA from ALTERA placed on education and development board DE-1. The proposed demodulator has the following parameters: =50MHz.CLKClock frequency: F- / K=50000 KHz /1250 =40 KHz ).CLK= Fsam: (fKHz= 40samSampling frequency : f- =2 KHzcutf:)low pass filter (LPFdigitaloff frequency of the-Cut- -Modulation type of signal is: BPSK .
<= fcut ).mod1,25 KHz ( f=0.12mod2fKHz or52=0.mod1f:frequencywithsquare pulseThe modulating signal is- KHz.=2carf:Carrier type: is sinusoidal with frequency- -The ROM capacity for the stored signal samples (8192X8 ) bits, and their values are positive within the range from 0 to 255.
-Frequency range: (3 Hz…25 MHz).
-Frequency Resolution: (3 Hz).
- Signal amplitude (5V).
-Using FPGA allows for the modification and development of the digital design to suit the designer's wishes and goals.

Keywords: digital demodulator , BPSK , DDFS , FPGA