Abstract:
This paper proposes the design and implementation of the mechanism of digital synthesizing for BPSK pulses according to Barker codes of 5, 7, 11, and 13 chips practically using a digital programmable device Cyclone II EP2C20F484C7 FPGA from ALTERA, placed on education and development board DE-1 according to the following parameters:
- The carrier frequency: F_c=1 MHz .
- Modulation type: BPSK according to Barker code.
- Sampling frequency :(F_samp=50 MHz ,T_samp=0.02 μsec).
- Pulse repetition period is : (T=200 μsec).
- Pulse width is : (τ=5 ,7 ,11 ,13 μsec).
- The single chip width is : (τ_CH=1μ sec⁡〖 ,F_CH=1 MHz〗 ).
- Chips number is : 5, 7, 11, and 13.
-Frequency resolution is : δf=762Hz.
- The results of the filter operation are studied using a digital oscilloscope GDS-1052U for the radar signal of the shown specifications.
-All variable parameters are computer – controlled, with BPSK or without BPSK, (f_0,N ,τ ,τ_CH ,T)

Keywords: BPSK , Barker Code , DDFS, FPGA.

Download: | DOI: 10.17148/IMRJR.2026.030204