Abstract: JIn this paper, we propose the design and implementation mechanism for a digital coherence BPSK demodulator based on the use of Direct Digital Frequency Synthesizer (DDFS) and digital filter using Cyclone II EP2C20F484C7 FPGA from ALTERA placed on education and development board DE-1. The proposed demodulator has the following parameters:
-Clock frequency: FCLK=50MHz.
-Sampling frequency : fsam= 40 KHz : (fsam= FCLK/ K=50000 KHz /1250 =40 KHz ).
-Cut- off frequency of the digital low pass filter (LPF) : fcut=2 KHz
-Modulation type of signal is: BPSK .
-The modulating signal is square pulse with frequency : fmod1=0.25 KHz or fmod2=0.125 KHz ( fmod1,2<= fcut ).
-Carrier type: is sinusoidal with frequency: fcar=2 KHz.
-The ROM capacity for the stored signal samples (8192X8 ) bits, and their values are positive within the range from 0 to 255.
-Frequency range: (3 Hz…25 MHz).
-Frequency Resolution: (3 Hz).
- Signal amplitude (5V).
-Using FPGA allows for the modification and development of the digital design to suit the designer's wishes and goals.

Keywords: digital demodulator , BPSK , DDFS , FPGA

Download: | DOI: 10.17148/IMRJR.2026.030303