Abstract: Digital signal filtering is used in many different fields, including communications, radar, navigation and others, because of its excellent performance and the ability to obtain accurate results using FIR and IIR filters.
In this paper, we propose the design and implementation mechanism for FIR digital BSF based on the use of Cyclone II EP2C20F484C7 FPGA from ALTERA, placed on education and development board DE-1. The designed filter has the following parameters:
-Clock frequency: FCLK=50 MHz.
-Sampling frequency: fsam= 2 MHz.
-Cut- off frequency of the band stop filter (BSF): fcut1=100 KHz , fcut2=200 KHz.
-Type of input signal is sinusoidal of frequency: finp1=50 KHz, finp2=100 KHz, , finp3=103 KHz , finp4=105 KHz , , finp5=150 KHz , finp6=200 KHz , finp7=203 KHz , finp8=205 KHz , finp9=250 KHz.
-The ROM capacity for the stored input signal samples is 8192X8 bits, and their values are positive within the range from
(0 to 255).
-Frequency range: (0.12 Hz…1 MHz).
-Frequency Resolution: (0.12 Hz).
- Signal amplitude (5V).
Digital designs using FPGA allow the system to be modified and developed to obtain better results through reprogramming according to the user's desire.

Keywords: digital filter, FIR, BSF, DDFS, FPGA.

| DOI: 10.17148/IMRJR.2025.020502