Abstract:
In this paper, we design a digital DSSS System using Cyclone II EP2C20F484C7 FPGA from ALTERA placed on education and development board DE-1 for the DSSS system with the transmitting and receiving sections according to the following parameters:
-Clock frequency of the system 10 KHz.
-Length of spreading pseudo-noise code (PNC): is (16) chips.
Type generation of spreading code: Walsh codes (H16).
-Length of data bit: is 3 bits with (16) chips for every one bit.
-spread operation: X
-Number of users: is eight.
-User 1 with Data (00) and pseudo-noise code:

Code 1= [ 1111111111111111]

1→+1 ,0→-1⟹ Code 1= [ 1111111111111111]

-User 2 with Data (01) and pseudo-noise code:
Code 2= [ 1010101010101010]

1→+1 ,0→-1⟹ Code 2= [ 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1]

-User 3 with Data (10) and pseudo-noise code:
Code 3= [ 1100110011001100]

1→+1 ,0→-1⟹ Code 3= [ 1 1 -1 -1 1 1 -1 -1 1 1 -1 -1 1 1 -1 -1]

-User 4 with Data (11) and pseudo-noise code:
Code 4= [ 1001100110011001]

1→+1 ,0→-1⟹ Code 4= [ 1 -1 -1 1 1 -1 -1 1 1 -1 -1 1 1 -1 -1 1]

-User 5 with Data (00) and pseudo-noise code:
Code 5= [ 1111000011110000]

1→+1 ,0→-1⟹ Code 5= [ 1 1 1 1 -1 -1 -1 -1 1 1 1 1 -1 -1 -1 -1]

-User 6 with Data (01) and pseudo-noise code:
Code 6= [ 1010010110100101]

1→+1 ,0→-1⟹ Code 6= [ 1 -1 1 -1 -1 1 -1 1 1 -1 1 -1 -1 1 -1 1]

-User 7 with Data (10) and pseudo-noise code:
Code 7= [ 1100001111000011]

1→+1 ,0→-1⟹ Code 7= [ 1 1 -1 -1 -1 -1 1 1 1 1 -1 -1 -1 -1 1 1]

-User 8 with Data (11) and pseudo-noise code:
Code 8= [ 1001011010010110]

1→+1 ,0→-1⟹ Code 8= [ 1 -1 -1 1 -1 1 1 -1 1 -1 -1 1 -1 1 1 -1]

These codes must be orthogonal to each other, so they are chosen according to Welch's codes via the HADAMARD matrix, for a (16-bit) codes, the H16 array should be chosen.

Keywords: CDMA, DSSS, Walsh Codes, PNC, PNCG, FPGA.

Download: | DOI: 10.17148/IMRJR.2025.021102