Design And Implementation Of a Digital Pseudo-Noise Walsh codes Using FPGA

Abstract: This paper presents the design and implementation of Walsh code generators with lengths of (8), (16), and (32-bits) bits using shift registers on a Cyclone II EP2C20F484C7 FPGA from ALTERA placed on education and development board DE-1. Walsh codes, as orthogonal sequences, enable efficient multi-user direct-sequence spread spectrum (DSSS) communication by minimizing cross-user interference. The core contribution is a shift-register-based generator architecture that outputs Walsh codes in a synchronized manner with the system clock, enabling scalable multi- user support while maintaining low resource usage on the Cyclone II FPGA. The work includes HDL descriptions, synthesis considerations on DE-1, and verification through functional and timing tests, demonstrating reliable code generation across all specified lengths and straightforward extension to additional lengths if required. The results indicate that the proposed approach provides a compact, deterministic, and easily verifiable implementation suitable for education, prototyping, and small-scale DSSS experiments.

Keywords: DSSS, Walsh Codes, PNWCG, FPGA.